1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a plurality of wiring formed to space apart from each other and a method of manufacturing the same.
2. Description of the Prior Art
In semiconductor integrated circuit devices, multi-layered wiring and high density wiring have been required according to high integration of the device.
Since an uneven surface of an interlayer insulating film is readily formed in the multilayered wiring structure, a wiring formed on the interlayer insulating film must be prevented from being cut off by reducing differences in the unevenness. In general, as a method of preventing the cut-off of the wiring, the upper surface of the interlayer insulating film has been planarized.
Usually planarization of the interlayer insulating film is effected by following steps.
As shown in a plan view of FIG. 1A, plural lower wiring 3 are first formed in parallel on a base insulating film 2 formed on a surface of a semiconductor substrate 1. Then, an SiO.sub.2 film 4 serving as the interlayer insulating film is formed on an entire surface of the semiconductor substrate 1 by CVD process. In this case, as shown in a sectional view of FIG. 1B, the SiO.sub.2 film 4 is grown on both surfaces of the base insulating film 2 and the wiring 3. For this reason, an uneven surface shape is generated on the SiO.sub.2 film 4 according to the surface unevenness of the base insulating film 2 and the wiring 3.
Subsequently, silicon compound containing solution is coated on the SiO.sub.2 film 4 by rotational coating. Then, solvent in the solution is removed by heating process. As a result, the surface of the SiO.sub.2 film 4 is covered by a SOG (Spin On Glass) film 5 which is made of silicon compound and has an even surface. Subsequently, the SOG film 5 is etched back so as to be left partially on concave portions of the SiO.sub.2 film 4. Both the SiO.sub.2 film 4 and the SOG film 5 serve as the interlayer insulating film so that an even surface of the interlayer insulating film can be derived. Then, the SiO.sub.2 film (not shown) is formed as a second layer by CVD process. A upper wiring (not shown) is formed on the second layer SiO.sub.2 film.
In the meanwhile, since the insulating film 4 formed between the wiring 3, 3 serves as a dielectric film of a capacitor, wiring capacitance (parasitic capacitance) exists between two of the wiring 3.
The wiring capacitance C can be obtained according to following equation (1). The wiring capacitance C is proportional to a relative dielectric constant of the insulating film 4 located between two of the wirings 3, and is inversely proportional to an interval d between the wiring 3. In general, the relative dielectric constant of the SiO.sub.2 is about 4 to 5. In the equation (1), .epsilon..sub.0 denotes dielectric constant in vacuum, .epsilon..sub.r denotes relative dielectric constant, and S denotes an area of a side surface of the wiring 3. EQU C=.epsilon..sub.0 .epsilon.rS/d (1)
The interval d between the wiring 3, 3 becomes short and a multilayered structure of the wiring is advanced as high integration of the semiconductor integrated circuit device proceeds. As a result, the wiring capacitance is increased and thus an operation of the semiconductor device is further delayed.